project.name

Siddhartha tyagi

Member since: 2 years

Educational Institution: AJAY KUMAR GARG ENGINEERING COLLEGE ,GHAZIABAD

Country: Not Entered

3*8 DECODER

3*8 DECODER
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2*4 DECODER 4*1 MUX 8*1MUX

2*4 DECODER 4*1 MUX 8*1MUX
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binary and grey converter

binary and grey converter
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HALF ADDER

HALF ADDER
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FULL ADDER LOGIC UNIT 1 BIT ALU

FULL ADDER LOGIC UNIT 1 BIT ALU
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4-bit CLA

4-bit CLA
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3*8 DECODER

3*8 DECODER
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ASS 3 : 3*8 decoder

ASS 3 : 3*8 decoder
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control unit hardwired

control unit hardwired
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4*16 Decoder

4*16 Decoder
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register language transfer

register language transfer
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S-R fLIP FLOP

S-R fLIP FLOP
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2*4 DECODER 4*1 MUX 8*1MUX

2*4 DECODER 4*1 MUX 8*1MUX
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Graphic Display v1

Graphic Display v1
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Siddhartha tyagi is not a collaborator of any project.

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