PC logic (automatically +1, unless modified by bezR0)
ALU: supporting {add, slt} operations.
Register File: containing R0 - R3 with 2 read ports and 1 write port.
Control Unit: able of generating corresponding MUX selection signals based on instruction opcode.
Top-level System IO:
System input: 1-bit input serving as clock signal.
A reset signal to clear PC = 0.
System output: various displays (can include hex LEDs) for the content of PC and each register.
Created:
Nov 05, 2023
Updated:
Nov 20, 2023
Add members
Enter Email IDs separated by commas, spaces or enter. Users need to be registered already on the platform. Note that collaboration is not real time as of now. Every save overwrites the previous data.
Delete
Are you sure you want to delete this project?
Delete
Are you sure you want to remove this collaborator?
Comments