Ashish Gupta
Member since: 2 years
Educational Institution: Not Entered
Country: Not Entered
8:1 MUX using 4:1 MUX & 2:1 MUX
8:1 MUX using 4:1 MUX & 2:1 MUX
Public
16:1 MUX using 8:1 MUX
16:1 MUX using 8:1 MUX
Public
2:4 decoder using 1:2 decoder
2:4 decoder using 1:2 decoder
Public
AOI logic circuit of 2:4 Decoder
AOI logic circuit of 2:4 Decoder
Public
AOI logic circuit of 4:2 encoder
AOI logic circuit of 4:2 encoder
Public
1x16 decoder
1x16 decoder
Public
NAND logic circuit of 2:4 Decoder
NAND logic circuit of 2:4 Decoder
Public
SOP F'(ABCD)
SOP F'(ABCD)
Public
F ABC' +D
F ABC' +D
Public
F pqrs
F pqrs
Public
ques 3 A LMN
ques 3 A LMN
Public
ques 3 B f xyz nand
ques 3 B f xyz nand
Public
u v w x QUES 4
u v w x QUES 4
Public
QUES 4 B
QUES 4 B
Public
Ques 5
Ques 5
Public
21BCE0569
21BCE0569
Public
4-bit_adder
4-bit_adder
Public
4-bit_adder
4-bit_adder
Public
multiplier
multiplier
Public
multiplier
multiplier
Public
Full Adder/Subtractor using Decoder
Full Adder/Subtractor using Decoder
Public
Full Adder/Subtractor using Decoder
Full Adder/Subtractor using Decoder
Public
mux viva 2
mux viva 2
Public
4 BIT ALU
4 BIT ALU
Public
viva 2
viva 2
Public
DA1
DA1
Public
SOP F(ABCD)
SOP F(ABCD)
Public
SOP F(ABCD)
SOP F(ABCD)
Public
Task 1 Half Adder (SOP)
Task 1 Half Adder (SOP)
Public
mux
mux
Public
1 BIT ALU
1 BIT ALU
Public
3*8 decoder using 2*4 decoder
3*8 decoder using 2*4 decoder
Public
4 :1 multiplexer using 2:1 Multiplexers
4 :1 multiplexer using 2:1 Multiplexers
Public
Task 1 Half Adder (SOP)
Task 1 Half Adder (SOP)
Public
