Ayan Acharya 21BCT0010
Member since: 2 years
Educational Institution: Not Entered
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Implementation steps for Task I and II using 4:1 Multiplexer
Implementation steps for Task I and II using 4:1 Multiplexer
CAT 1 Q5
CAT 1 Q5
CAT1 Q4
CAT1 Q4
21BCT0010 1-bit ALU
21BCT0010 1-bit ALU
F SOP circuit in AND-OR -INV logic
F SOP circuit in AND-OR -INV logic
6 bit comparator
6 bit comparator
8:1 MUX using 4:1 MUX
8:1 MUX using 4:1 MUX
3:8 DECODER using 2:1 DECODER
3:8 DECODER using 2:1 DECODER
Full Adder using 4:1 Mux
Full Adder using 4:1 Mux
NAND logic circuit of 4:2 encoder
NAND logic circuit of 4:2 encoder
F' NOR logic
F' NOR logic
AOI logic circuit of 2:4 Decoder
AOI logic circuit of 2:4 Decoder
Full Adder using 8:1 MUX
Full Adder using 8:1 MUX
Implementation of Task 1 for 21BCT0010
Implementation of Task 1 for 21BCT0010
Full Subtractor with a 3:8 Decoder
Full Subtractor with a 3:8 Decoder
NAND logic circuit of 2:4 Decoder
NAND logic circuit of 2:4 Decoder
AOI logic circuit of 4:2 encoder
AOI logic circuit of 4:2 encoder
2:1 MUX Circuit using SOP Equation using NAND
2:1 MUX Circuit using SOP Equation using NAND
2:1 MUX Circuit using POS Equation using NOR
2:1 MUX Circuit using POS Equation using NOR
F' NAND logic
F' NAND logic
F' POS circuit in OR-AND -INV logic
F' POS circuit in OR-AND -INV logic
F' SOP circuit in AND-OR -INV logic
F' SOP circuit in AND-OR -INV logic
Adder from full adder
Adder from full adder
4 bit ALU_21BCT0010
4 bit ALU_21BCT0010
2:4 Decoder using 1:2 Decoder
2:4 Decoder using 1:2 Decoder
F NAND logic
F NAND logic
F NOR logic
F NOR logic
4X4 MULTIPLIER
4X4 MULTIPLIER
Full bit adder using logic gates
Full bit adder using logic gates
21BCT0010_SET_A_Q53
21BCT0010_SET_A_Q53
21BCT0010_SET_B_Q53
21BCT0010_SET_B_Q53
21BCT0010-1-BIT-ALU
21BCT0010-1-BIT-ALU
Full Adder using 3:8 decoder
Full Adder using 3:8 decoder
2:1 MUX Circuit using POS Equation
2:1 MUX Circuit using POS Equation
CAT Q3
CAT Q3
CAT 1 Q1
CAT 1 Q1
CAT Q3
CAT Q3
CAT 1 Q5
CAT 1 Q5
CAT1 Q4
CAT1 Q4
SET B HOTS QUESTION
SET B HOTS QUESTION
Universal shift register 21BCT0010
Universal shift register 21BCT0010
COMMON ANODE 7 SEGMENT DECODER
COMMON ANODE 7 SEGMENT DECODER
Untitled
Untitled
COMMON CATHODE 7 SEGMENT DECODER_16:1 MUX
COMMON CATHODE 7 SEGMENT DECODER_16:1 MUX
16*1 mux using 4*1 mux
16*1 mux using 4*1 mux
8:1 MUX using 4:1 MUX
8:1 MUX using 4:1 MUX
8:1 MUX using 4:1 MUX
8:1 MUX using 4:1 MUX
8:1 MUX using 4:1 MUX
8:1 MUX using 4:1 MUX
8:1 mux using 2:1 mux
8:1 mux using 2:1 mux
7 segmen decoder using 8:1 mux
7 segmen decoder using 8:1 mux
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
decoder using demultiplexer
decoder using demultiplexer
BCD to 8124 converter
BCD to 8124 converter
BCD ripple counter
BCD ripple counter
asynchronous counter
asynchronous counter
asynchronous counter
asynchronous counter
Mealy Machine
Mealy Machine
Mealy Machine
Mealy Machine
Moore Machine
Moore Machine
Moore Machine
Moore Machine
4-bit Magnitude comparator
4-bit Magnitude comparator
4-bit Magnitude comparator
4-bit Magnitude comparator
2:1 MUX Circuit using SOP Equation
2:1 MUX Circuit using SOP Equation
Seven segment decoder circuit
Seven segment decoder circuit
Seven segment decoder circuit
Seven segment decoder circuit
Implementation of Task 1 for 21BCT0010 using 4:1 Multiplexer
Implementation of Task 1 for 21BCT0010 using 4:1 Multiplexer
COMMON ANODE 7 SEGMENT DECODER
COMMON ANODE 7 SEGMENT DECODER
16:1 MUX using 8:1 MUX
16:1 MUX using 8:1 MUX
3X3 MULTIPLIER
3X3 MULTIPLIER
Full Subtractor using 8:1 MUX
Full Subtractor using 8:1 MUX
4:1 MUX using 2:1 MUX
4:1 MUX using 2:1 MUX
16*1 mux using 4*1 mux
16*1 mux using 4*1 mux
Full Subtractor using 4:1 Mux
Full Subtractor using 4:1 Mux
BCD ripple counter
BCD ripple counter
F POS circuit in OR-AND -INV logic
F POS circuit in OR-AND -INV logic
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
2x2 MULTIPLIER
2x2 MULTIPLIER
BCD To 7 Segment Decoder
BCD To 7 Segment Decoder
4-Bit Synchronous Up Counter
4-Bit Synchronous Up Counter
4-Bit Synchronous Up Counter
4-Bit Synchronous Up Counter
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