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4:16_decoder
4:16_decodercoomon_anode_dc
coomon_anode_dchalf_adder_21bce2911
half_adder_21bce2911DA_4_AND_OR
DA_4_AND_ORQ1_b
Q1_bQ3_a
Q3_aQ3(b)
Q3(b)Q4_b
Q4_bQ5_1
Q5_1q4_a
q4_afull_adder_21bce2911
full_adder_21bce2911full_subtractor_21bce2911
full_subtractor_21bce2911practice_16x1
practice_16x1Full Adder using Half Adder using mux Using Mux
Full Adder using Half Adder using mux Using Muxhs_21bce2911
hs_21bce29112x1_mux_using_nor
2x1_mux_using_nor16x1_using_8x1_and_2x1
16x1_using_8x1_and_2x14x1_using_2x1
4x1_using_2x1half_adder_using_decoder
half_adder_using_decoder3x8_using_2x4_decoder
3x8_using_2x4_decodert1_34_21bce2911_1
t1_34_21bce2911_1t1_34_21bce2911_pos_nor
t1_34_21bce2911_pos_nort1_34_21bce2911
t1_34_21bce2911Task_2_example
Task_2_examplet1_34_21bce2911_SOP2
t1_34_21bce2911_SOP24-bit ALU
4-bit ALUT1_34_VIVA_CIRCUIT_21BCE2911
T1_34_VIVA_CIRCUIT_21BCE2911VIVA_34_21BCE2911_Q2
VIVA_34_21BCE2911_Q24:2 Encoder
4:2 EncoderT1_34_21BCE2911_VIVA_Q1
T1_34_21BCE2911_VIVA_Q1T1_34_21BCE2911_Q2
T1_34_21BCE2911_Q22x1_using_and_or
2x1_using_and_or1_BIT_ALU
1_BIT_ALU2x1_SOP
2x1_SOP2x1_mux_POS
2x1_mux_POS2X1_mux_nand
2X1_mux_nandimplement_16x1_t1_t2
implement_16x1_t1_t22:4 Decoder using NAND
2:4 Decoder using NAND3*8 DECODER USING TWO 2*4 DECODERS
3*8 DECODER USING TWO 2*4 DECODERSFull Adder using Decoder
Full Adder using Decoder4-bit ALU
4-bit ALUDeMux 1:4
DeMux 1:47 Segment Display
7 Segment DisplayDA_3_NAND
DA_3_NAND7_SEG_MUX_CATHODE
7_SEG_MUX_CATHODE8X1_mux_7_segment
8X1_mux_7_segment4-bit Magnitude comparator
4-bit Magnitude comparatorMealy_machines
Mealy_machinesMoore_machine
Moore_machineSynchron_ctr
Synchron_ctrAynchr_ctr
Aynchr_ctrSEVEN SEGMENT DECODER CIRCUITCOMMON ANODE
SEVEN SEGMENT DECODER CIRCUITCOMMON ANODE8:1 MUX using 2:1 MUX
8:1 MUX using 2:1 MUXCOMMON CATHODE 7 SEGMENT DECODER_16:1 MUX
COMMON CATHODE 7 SEGMENT DECODER_16:1 MUXCOMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUX
COMMON ANODE SEVEN SEGMENT DECODER USING 16:1 MUXwithout_dc_cathode
without_dc_cathodeQ3_HOT_QUES_CIRCUITVERSE
Q3_HOT_QUES_CIRCUITVERSEImplement a Combinational circuit framed by reg no 8:1 mux
Implement a Combinational circuit framed by reg no 8:1 mux8 BIT ALU
8 BIT ALU3:8_decoder
3:8_decodert1_34_21bce2911_pos_1
t1_34_21bce2911_pos_1Untitled
Untitled8 BIT ALU
8 BIT ALU2x4_Decoder_using_AOI
2x4_Decoder_using_AOI2x2_multiplier_21bce2911
2x2_multiplier_21bce2911Implementation of combinational circuit using 16:1 mux:(1,2,9,11,12,14)
Implementation of combinational circuit using 16:1 mux:(1,2,9,11,12,14)LAB 10
LAB 10