project.name

VIDHYASHREE V

Member since: 1 year

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20211CAI0081 3

20211CAI0081 3
Public
20211CAI0081 3

Untitled

Untitled
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Untitled

4:1 MUX using NAND

4:1 MUX using NAND
Public
4:1 MUX using NAND

2:1 MUX using NAND

2:1 MUX using NAND
Public
2:1 MUX using NAND

20211cai0081experiment 1

20211cai0081experiment 1
Public
20211cai0081experiment 1

4:1 MUX

4:1 MUX
Public
4:1 MUX

4:1 MUX

4:1 MUX
Public
4:1 MUX

1:2 DEMUX using NAND

1:2 DEMUX using NAND
Public
1:2 DEMUX using NAND

Untitled

Untitled
Public
Untitled

Untitled

Untitled
Public
Untitled

Untitled

Untitled
Public
Untitled

4:2 Priority encoder

4:2 Priority encoder
Public
4:2 Priority encoder

20211CAI0081__2

20211CAI0081__2
Public
20211CAI0081__2

Untitled

Untitled
Public
Untitled

1:2 DEMUX

1:2 DEMUX
Public
1:2 DEMUX

1:4 DE-MULTIPLEXER

1:4 DE-MULTIPLEXER
Public
1:4 DE-MULTIPLEXER

4:2 Priority encoder

4:2 Priority encoder
Public
4:2 Priority encoder

4:2 Bit Binary Encoder

4:2 Bit Binary Encoder
Public
4:2 Bit Binary Encoder

experiment 3

experiment 3
Public
experiment 3

logic diagram using NAND Gates

logic diagram using NAND Gates
Public
logic diagram using NAND Gates
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VIDHYASHREE V is not a collaborator of any project.