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Adithya V

Member since: 2 years

Educational Institution: Not Entered

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Full Subtractor using X-OR and NAND

Full Subtractor using X-OR and NAND
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Half Subtractor using NAND only

Half Subtractor using NAND only
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Experiment 5

Experiment 5
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Experiment 7

Experiment 7
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2:1 MUX using NAND and 4:1 MUX using NAND

2:1 MUX using NAND and 4:1 MUX using NAND
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Basic gates realisation of 2:1 MUX and Basic gates realisation of 4:1 MUX

Basic gates realisation of 2:1 MUX and Basic gates realisation of 4:1 MUX
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Full Adder using X-OR and NAND

Full Adder using X-OR and NAND
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Half Adder using NAND only

Half Adder using NAND only
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Full Adder using NAND only

Full Adder using NAND only
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1:2 DEMUX using NAND and 1:4 DEMUX using NAND

1:2 DEMUX using NAND and 1:4 DEMUX using NAND
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Half Adder using X-OR and NAND

Half Adder using X-OR and NAND
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Realisation of 1:4 DEMUX using Basic gates

Realisation of 1:4 DEMUX using Basic gates
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Full Subtractor using NAND only

Full Subtractor using NAND only
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Half Subtractor using X-OR and NAND

Half Subtractor using X-OR and NAND
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