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20211CSD0102 (EXPO-01)
20211CSD0102 (EXPO-01)20211CSD0102 (EXPO-2)
20211CSD0102 (EXPO-2)DE-MORGANS FIRST LAW
DE-MORGANS FIRST LAWDE-MORGAN SECOND LAW
DE-MORGAN SECOND LAWy=[(u+x`)(y`+z)] logic diaram to implement boolean
y=[(u+x`)(y`+z)] logic diaram to implement booleanENCODER
ENCODERUntitled
UntitledHALF SUBTRACTOR
HALF SUBTRACTORCOMBINATION OF ADDER
COMBINATION OF ADDERDEMULTIPLEX
DEMULTIPLEXNAND GATE USING UNIVERSAL GATE
NAND GATE USING UNIVERSAL GATE