project.name

JASEEL FAYIS P K

Member since: 2 years

Educational Institution: Not Entered

Country: Not Entered

XOR GATE FOR VERILOG

XOR GATE FOR VERILOG
Public
project.name

ALU NEW

ALU NEW
Public
project.name

XOR GATE USING NAND GATE FOR VERILOG

XOR GATE USING NAND GATE FOR VERILOG
Public
project.name

ALL LOGIC GATE

ALL LOGIC GATE
Public
project.name

AND gate subcircuit

AND gate subcircuit
Public
project.name

NOT Gate for verilog

NOT Gate for verilog
Public
project.name

OR Gate for Verilog

OR Gate for Verilog
Public
project.name

AND Gate for verilog

AND Gate for verilog
Public
project.name

NAND Gate for verilog

NAND Gate for verilog
Public
project.name

NOR GATE USING LOGIC GATES

NOR GATE USING LOGIC GATES
Public
project.name

OR GATE USING NAND GATE

OR GATE USING NAND GATE
Public
project.name

AND GATE USING NOR GATE

AND GATE USING NOR GATE
Public
project.name

AND GATE USING NAND GATE

AND GATE USING NAND GATE
Public
project.name

XOR GATE USING NOR GATE

XOR GATE USING NOR GATE
Public
project.name

NAND Gate using logic gate for veilog

NAND Gate using logic gate for veilog
Public
project.name

XNOR GATE FOR VERILOG

XNOR GATE FOR VERILOG
Public
project.name

XNOR GATE USING NAND GATE

XNOR GATE USING NAND GATE
Public
project.name

OR GATE USING NOR GATE

OR GATE USING NOR GATE
Public
project.name

NOT GATE USING NOR GATE

NOT GATE USING NOR GATE
Public
project.name

XOR GATE USING LOGIC GATES FOR VERILOG

XOR GATE USING LOGIC GATES FOR VERILOG
Public
project.name

NOR GATE FOR VRILOG

NOR GATE FOR VRILOG
Public
project.name

XNOR GATE USING NOR GATE

XNOR GATE USING NOR GATE
Public
project.name

NOT GATE USING NAND GATE

NOT GATE USING NAND GATE
Public
project.name

MULTIPLEXERS

MULTIPLEXERS
Public
project.name

ADDER SUBTRACTOR CIRCUITS

ADDER SUBTRACTOR CIRCUITS
Public
project.name

SUBTRACTOR CIRCUIT

SUBTRACTOR CIRCUIT
Public
project.name

ADDER CIRCUITS

ADDER CIRCUITS
Public
project.name

32 BIT FULL ADDER USING ONLY 4 BIT FULL ADDER

32 BIT FULL ADDER USING ONLY 4 BIT FULL ADDER
Public
project.name

LOGIC GATES USING MUX

LOGIC GATES USING MUX
Public
project.name

Untitled

Untitled
Public
project.name

ALU

ALU
Public
project.name

32 bit 4 bit

32 bit 4 bit
Public
project.name

ALU

ALU
Public
project.name

A_L_U

A_L_U
Public
project.name

ALU

ALU
Public
project.name

ALU

ALU
Public
project.name

A L U

A L U
Public
project.name

ALU 1 (All FlipFlop)

ALU 1 (All FlipFlop)
Public
project.name

Registers

Registers
Public
project.name

Counters

Counters
Public
project.name

Add/sub

Add/sub
Public
project.name

Main ALU

Main ALU
Public
project.name

XNOR GATE USING LOGIC GATES FOR VERILOG

XNOR GATE USING LOGIC GATES FOR VERILOG
Public
project.name
No result image
JASEEL FAYIS P K doesn't have any favourites.
No result image
JASEEL FAYIS P K is not a collaborator of any project.