project.name

Shelendra Jadon

Member since: 2 years

Educational Institution: Banaras Hindu University

Country: India

assignment-3 (2)

assignment-3 (2)
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assignment-3 (1)

assignment-3 (1)
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assignment-3 ,4

assignment-3 ,4
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assingment-3,3

assingment-3,3
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3.4

3.4
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COUNTER

COUNTER
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SR latch using NAND gate

SR latch using NAND gate
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ASSINMENT 8 MUX 4

ASSINMENT 8 MUX 4
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ASSIGNMENT 8 (2)

ASSIGNMENT 8 (2)
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0R gate with 32 input

0R gate with 32 input
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DECODER 2*4

DECODER 2*4
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5*32 DECODER (using 3*8 and 2*4 decoder

5*32 DECODER (using 3*8 and 2*4 decoder
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ASSIGNMENT 8 (4)

ASSIGNMENT 8 (4)
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ASSINGMENT 5 (1)

ASSINGMENT 5 (1)
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ASSIGNMENT 9 (3)

ASSIGNMENT 9 (3)
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ASSIGNMENT 5 (2)

ASSIGNMENT 5 (2)
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ASSINGMENT 5 (3)

ASSINGMENT 5 (3)
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ASSIGNMENT 9 (2)

ASSIGNMENT 9 (2)
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ASSIGNMENT 9 (6)

ASSIGNMENT 9 (6)
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ASSIGNMENT 9 (4)

ASSIGNMENT 9 (4)
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ASSIGNMENT 9 (5)

ASSIGNMENT 9 (5)
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Untitled

Untitled
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Untitled

Untitled
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ASSIGNMENT 5 (4)

ASSIGNMENT 5 (4)
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ASSIGNMENT 6(2)

ASSIGNMENT 6(2)
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ASSIGNMENT 6 (1)

ASSIGNMENT 6 (1)
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ASSIGNMENT 9 (6)

ASSIGNMENT 9 (6)
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assig2,2

assig2,2
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assig-2,4

assig-2,4
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assig2,2

assig2,2
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Untitled

Untitled
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assig2,3

assig2,3
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assig-2,6(b)

assig-2,6(b)
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assig-3,6

assig-3,6
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assig-2,6(b)\

assig-2,6(b)\
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assig-2,7

assig-2,7
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assig-2,5

assig-2,5
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CCCCCC

CCCCCC
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COUNTER

COUNTER
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5*32 DECODER (using 3*8 decoder)

5*32 DECODER (using 3*8 decoder)
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project.name
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Binary parallel adder of 4 bit no.

Binary parallel adder of 4 bit no.
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