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A3.1
A3.1A3.2
A3.2A3.3
A3.3A3.4
A3.4A4.1
A4.1A4.2
A4.2sequential circuit with JK flip flop
sequential circuit with JK flip flopmux
mux2X4 Decoder&16bit ROM& combinational circuit
2X4 Decoder&16bit ROM& combinational circuitA5.1
A5.1A5.4
A5.4A5.3
A5.3ABCD
ABCDSSVcircuitverse
SSVcircuitverseA5.2
A5.2A6.1
A6.1A6.2
A6.2S R latch
S R latchs R latch with CP using NAND gate
s R latch with CP using NAND gateD flip flop
D flip flopJ K flip flop
J K flip flopT flip flop
T flip flopsequential circuit using D flip flop
sequential circuit using D flip flopsimple CPU
simple CPUExclusive OR
Exclusive ORAND GATE
AND GATENAND GATE
NAND GATEPratham Maheshwari/Verify the excitation tables of various FLIP-FLOPS.
Pratham Maheshwari/Verify the excitation tables of various FLIP-FLOPS.Verify the excitation tables of various FLIP-FLOPS.
Verify the excitation tables of various FLIP-FLOPS.s r latch using nor gate
s r latch using nor gatekMAPvsTabulation
kMAPvsTabulationUntitled
UntitledA7.1
A7.1Half Adder
Half AdderUntitled
UntitledA7.6
A7.6A7.4
A7.4A7.3
A7.3A7.5
A7.5A7.2
A7.2NOT gate using NOR gate
NOT gate using NOR gateOR gate using NOR gate
OR gate using NOR gateUntitled
Untitledgates using nor gate
gates using nor gateNAND GATE
NAND GATEgates using nand gate
gates using nand gategates
gatesxor/xnor using basic gates
xor/xnor using basic gatesgate1
gate1