project.name

Lab

Member since: 2 years

Educational Institution: Not Entered

Country: Not Entered

HALF Adder

HALF Adder
Public
project.name

Full adder

Full adder
Public
project.name

Half Subtractor

Half Subtractor
Public
project.name

Full Subtractor

Full Subtractor
Public
project.name

4 to 2 Encoder

4 to 2 Encoder
Public
project.name

3:8 Decoder

3:8 Decoder
Public
project.name

1*4 DEMULTIPLEXER

1*4 DEMULTIPLEXER
Public
project.name

4 Bit Parallel Adder

4 Bit Parallel Adder
Public
project.name

JK FLIP FLOP

JK FLIP FLOP
Public
project.name

T Flip Flop

T Flip Flop
Public
project.name

8:1 Mux using Logic Gates

8:1 Mux using Logic Gates
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

D Flip-Flop

D Flip-Flop
Public
project.name

4-bit Parallel Adder

4-bit Parallel Adder
Public
project.name

4×1 MUX

4×1 MUX
Public
project.name

SR Flip Flop

SR Flip Flop
Public
project.name

2:4 Decoder

2:4 Decoder
Public
project.name

8:3 Encoder

8:3 Encoder
Public
project.name
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