project.name

Álvaro

Member since: 426 days

Educational Institution: Not Entered

Country: Not Entered

Proyect P1 18.11.2019

Public
Proyect P1 18.11.2019

Counter

Public
Counter

RAMs up to 8 bits, synchronous or always enabled output

Public
RAMs up to 8 bits, synchronous or always enabled output

BCD to 7dig displ

Public
BCD to 7dig displ

Hamming(7,4)

Public
Hamming(7,4)

Comparators, 2 bit, 4 bit, 8 bit

Public
Comparators, 2 bit, 4 bit, 8 bit

Displacement register

Public
Displacement register

Up to 8bit ALU , Full-adder plus CA2 subtraction

Public
Up to 8bit ALU , Full-adder plus CA2 subtraction

BCD

Public
BCD