Dhruv Malhotra
Member since: 2 years
Educational Institution: Not Entered
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1 - bit alu many to one
1 - bit alu many to one
1x8 demux
1x8 demux
4X1 MULTIPLEXER
4X1 MULTIPLEXER
4X1 MULTIPLEXER
4X1 MULTIPLEXER
DE - MULTIPLEXER
DE - MULTIPLEXER
ENCODER VIT
ENCODER VIT
Full adder using 2x1 MUX
Full adder using 2x1 MUX
DECODER VIT
DECODER VIT
Full adder using 2x1 MUX
Full adder using 2x1 MUX
ENCODER VIT
ENCODER VIT
8X3 DECODER
8X3 DECODER
4 Bit ALU using 1 Bit ALU
4 Bit ALU using 1 Bit ALU
32 to 1 mux using 4 to 1 mux
32 to 1 mux using 4 to 1 mux
BINARY LEFT AND RIGHT SHIFT
BINARY LEFT AND RIGHT SHIFT
3 - BIT multiplication algorithum
3 - BIT multiplication algorithum
Full adder using 2x1 MUX
Full adder using 2x1 MUX
BINARY LEFT AND RIGHT SHIFT
BINARY LEFT AND RIGHT SHIFT
2 BIT ADD/SUB ALGO
2 BIT ADD/SUB ALGO
L4
L4
4 bit memory register w/ D Flip Flop
4 bit memory register w/ D Flip Flop
DECODER VIT
DECODER VIT
Flip-Flops using NAND Gate
Flip-Flops using NAND Gate
1 - bit alu many to one
1 - bit alu many to one
1 - bit alu many to one
1 - bit alu many to one
model lab fat 4 times right shift
model lab fat 4 times right shift
Demultiplexer
Demultiplexer
4 Bit ALU using 1 Bit ALU
4 Bit ALU using 1 Bit ALU
3 - BIT multiplication algorithum
3 - BIT multiplication algorithum
2 BIT ADD/SUB ALGO
2 BIT ADD/SUB ALGO
2 BIT ADD/SUB ALGO
2 BIT ADD/SUB ALGO
JK FlipFlop using AND and NOR Gates
JK FlipFlop using AND and NOR Gates
Demultiplexer
Demultiplexer
LAB 4
LAB 4
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