project.name

Emerson

Member since: 2 years

Educational Institution: Not Entered

Country: Not Entered

D FF with NORs

D FF with NORs
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Up/Down counter

Up/Down counter
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Full-Step

Full-Step
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mod60

mod60
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4 bit togl sync counter

4 bit togl sync counter
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ass2

ass2
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Half-Step

Half-Step
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De Morgan's Laws Proof

De Morgan's Laws Proof
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Multiplexer logic gate

Multiplexer logic gate
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2 to 1 Multiplexer

2 to 1 Multiplexer
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Half Adder using Multiplexers

Half Adder using Multiplexers
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Prime Detector

Prime Detector
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Prime Multiplex

Prime Multiplex
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NAND Latch

NAND Latch
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Lab 5

Lab 5
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circuit

circuit
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assignment

assignment
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Temp alarm

Temp alarm
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sc ff

sc ff
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NAND Latch

NAND Latch
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