Member since: 3 years
Educational Institution: President University
Country: Indonesia
EEPROM
EEPROMEEPROM
EEPROMCOA_CV
COA_CVLogic Devices
Logic DevicesD Latch and Asynchronous Register
D Latch and Asynchronous RegisterBasic Logic Gates
Basic Logic GatesALU
ALUFlip Flop
Flip Flop4 bits Adder and Subtractor
4 bits Adder and SubtractorAsynchronous Register Using Latch
Asynchronous Register Using Latchhex display
hex display16,11 Hamming Code
16,11 Hamming CodeCOA Week 2
COA Week 2MicroOperations
MicroOperationsPKM Half Adder
PKM Half AdderPKM Logic AND
PKM Logic ANDPKM Logic OR
PKM Logic ORPKM Full Adder
PKM Full AdderExercise PKM Sesi II
Exercise PKM Sesi IIPKM Full Adder 2 bit
PKM Full Adder 2 bitSynchronous Register Using D Flip Flop
Synchronous Register Using D Flip FlopUntitled
UntitledPKM Logic NOT
PKM Logic NOT16 Segment Display Example
16 Segment Display ExampleAdders
AddersTic_tac
Tic_tacExercise PKM Sesi I
Exercise PKM Sesi IBasic Gates
Basic GatesBasic Gates
Basic Gatesbinary to decimal
binary to decimalRAM
RAMCOA RAM ROM
COA RAM ROMAdder-Substractor
Adder-SubstractorShift
ShiftPKM Exercises
PKM ExercisesDS II HW 6 _ Controller Design
DS II HW 6 _ Controller DesignConstant Button
Constant ButtonJK Flip flop
JK Flip flopSequential Circuits
Sequential CircuitsT Flip Flop
T Flip FlopMaterials for Digital System Final Exam (Backup)
Materials for Digital System Final Exam (Backup)Digital System HW 4
Digital System HW 4Circuit_Simplification_Example
Circuit_Simplification_ExampleBasic Logic Gates_DigSys
Basic Logic Gates_DigSysQuiz 1 Problem 3
Quiz 1 Problem 3Digital System HW 4
Digital System HW 4For Quiz and Final
For Quiz and FinalDecoder
DecoderNAND-NAND Synthesis
NAND-NAND SynthesisAdders
AddersAdders
AddersMaterials for Digital System Final Exam
Materials for Digital System Final Exam