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Vanshika Sood

Member since: 3 years

Educational Institution: NIT Hamirpur

Country: India

d flip flop

d flip flop
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t ff

t ff
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jk ff

jk ff
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Half adder

Half adder
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Half adder

Half adder
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Verify DE Morgan's Law

Verify DE Morgan's Law
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Verify DE Morgan's Law

Verify DE Morgan's Law
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HALF SUBTRACTOR USING NOR GATE

HALF SUBTRACTOR USING NOR GATE
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4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
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HALF SUBTRACTOR USING NAND GATES

HALF SUBTRACTOR USING NAND GATES
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Full Subtractor using NOR Gate

Full Subtractor using NOR Gate
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Full Subtractor using NOR Gate

Full Subtractor using NOR Gate
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Full Subtractor using NOR gate

Full Subtractor using NOR gate
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Full Subtractor using NOR gate

Full Subtractor using NOR gate
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SR FF

SR FF
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Full Subtractor using NAND Gate

Full Subtractor using NAND Gate
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Wallace adder

Wallace adder
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4 bit carry look ahead

4 bit carry look ahead
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ALU

ALU
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ALU

ALU
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4 : 1 multiplexer

4 : 1 multiplexer
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lab 9

lab 9
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5 bit Ring counter

5 bit Ring counter
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5 bit synchronous binary counter

5 bit synchronous binary counter
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5 bit johnson counter

5 bit johnson counter
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5 bit johnson counter

5 bit johnson counter
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5 bit Ring counter

5 bit Ring counter
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5 bit synchronous binary counter

5 bit synchronous binary counter
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ALU

ALU
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ALU

ALU
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Full Adder using NAND Gates

Full Adder using NAND Gates
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Full Adder using NOR Gates

Full Adder using NOR Gates
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4 bit Ripple Carry Adder

4 bit Ripple Carry Adder
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5-bit Synchronous binary counter using JK flip flops

5-bit Synchronous binary counter using JK flip flops
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HALF SUBTRACTOR USING NAND GATES

HALF SUBTRACTOR USING NAND GATES
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5-bit Synchronous binary counter using JK flip flops

5-bit Synchronous binary counter using JK flip flops
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4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
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Vanshika Sood is not a collaborator of any project.

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