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Gate practice
Gate practiceUntitled
Untitled4-BIT BINARY ADDER/SUBTRACTER
4-BIT BINARY ADDER/SUBTRACTER3 - BIT multiplication algorithum
3 - BIT multiplication algorithum2 BIT ADD/SUB ALGO
2 BIT ADD/SUB ALGOBINARY LEFT AND RIGHT SHIFT
BINARY LEFT AND RIGHT SHIFTXOR using NOR gates
XOR using NOR gatesBasic gates using NAND GATE
Basic gates using NAND GATE4X1 MULTIPLEXER
4X1 MULTIPLEXER4X1 MULTIPLEXER
4X1 MULTIPLEXERDeMux 1:4
DeMux 1:4DeMux 1:4
DeMux 1:4Full Adder using 2, 4*1 MUX
Full Adder using 2, 4*1 MUXFull adder using 2x1 MUX
Full adder using 2x1 MUXFull adder using 2x1 MUX
Full adder using 2x1 MUXFull Adder using DEMUX
Full Adder using DEMUXFull Adder using DEMUX
Full Adder using DEMUX2 bit multiplier circuit
2 bit multiplier circuit8x3 Encoder
8x3 Encoder8x3 Encoder
8x3 Encoder8x3 encoder(exp7)
8x3 encoder(exp7)8x3 encoder(exp7)
8x3 encoder(exp7)8X3 ENCODER
8X3 ENCODER8X3 ENCODER
8X3 ENCODERHalf-Adder
Half-Adder4 bit memory register w/ D Flip Flop
4 bit memory register w/ D Flip FlopEXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXEREXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXEREXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXEREXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXEREXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXEREXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXERSR Flip Flop
SR Flip FlopSR Flip Flop
SR Flip FlopSR Flip Flop
SR Flip FlopClocked SR Flip Flop
Clocked SR Flip FlopClocked SR Flip Flop
Clocked SR Flip FlopL4
L4L4
L41:4 Demultiplexer using logic gates
1:4 Demultiplexer using logic gatesComputer Architecture - CPU Design
Computer Architecture - CPU DesignComputer Architecture - CPU Design
Computer Architecture - CPU DesignSIMPLE COMPUTER
SIMPLE COMPUTERSIMPLE COMPUTER
SIMPLE COMPUTER(4 to 2) line and (8 to 3) Line Encoders
(4 to 2) line and (8 to 3) Line Encoders4X1 MULTIPLEXER
4X1 MULTIPLEXERExperiment - 6 4 bit binary Adder/Subtractor
Experiment - 6 4 bit binary Adder/Subtractor2 BIT ADD/SUB ALGO
2 BIT ADD/SUB ALGO1:4 Demultiplexer using logic gates
1:4 Demultiplexer using logic gatesSpaghett MK 1
Spaghett MK 1Full Adder
Full Adder8 bit CPU
8 bit CPU4 BIT Memory
4 BIT MemoryBasic gates using NAND GATE
Basic gates using NAND GATE8 bit CPU
8 bit CPUMinimal ALU
Minimal ALU3 - BIT multiplication algorithum
3 - BIT multiplication algorithum5x32 Decoder using a combination of 2x4 Decoder and 3x8 Decoder
5x32 Decoder using a combination of 2x4 Decoder and 3x8 DecoderMinimal ALU
Minimal ALU(4 to 2) line and (8 to 3) Line Encoders
(4 to 2) line and (8 to 3) Line Encoders5x32 Decoder using a combination of 2x4 Decoder and 3x8 Decoder
5x32 Decoder using a combination of 2x4 Decoder and 3x8 DecoderBINARY LEFT AND RIGHT SHIFT
BINARY LEFT AND RIGHT SHIFT4 bit memory register w/ D Flip Flop
4 bit memory register w/ D Flip FlopXNOR GATE using NOR GATE
XNOR GATE using NOR GATE4-bit parallel adder/subtractor
4-bit parallel adder/subtractorCPU Microprocessor
CPU MicroprocessorSAP - 1
SAP - 1Spaghett MK 1
Spaghett MK 18:3 Encoder
8:3 EncoderCPU Microprocessor
CPU MicroprocessorSAP - 1
SAP - 18 bit CPU
8 bit CPU