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Anitej Sood

Member since: 2 years

Educational Institution: Not Entered

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Gate practice

Gate practice
Public
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Untitled

Untitled
Public
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4-BIT BINARY ADDER/SUBTRACTER

4-BIT BINARY ADDER/SUBTRACTER
Public
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3 - BIT multiplication algorithum

3 - BIT multiplication algorithum
Public
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2 BIT ADD/SUB ALGO

2 BIT ADD/SUB ALGO
Public
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BINARY LEFT AND RIGHT SHIFT

BINARY LEFT AND RIGHT SHIFT
Public
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XOR using NOR gates

XOR using NOR gates
Public
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Basic gates using NAND GATE

Basic gates using NAND GATE
Public
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4X1 MULTIPLEXER

4X1 MULTIPLEXER
Public
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4X1 MULTIPLEXER

4X1 MULTIPLEXER
Public
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DeMux 1:4

DeMux 1:4
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DeMux 1:4

DeMux 1:4
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Full Adder using 2, 4*1 MUX

Full Adder using 2, 4*1 MUX
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Full adder using 2x1 MUX

Full adder using 2x1 MUX
Public
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Full adder using 2x1 MUX

Full adder using 2x1 MUX
Public
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Full Adder using DEMUX

Full Adder using DEMUX
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Full Adder using DEMUX

Full Adder using DEMUX
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2 bit multiplier circuit

2 bit multiplier circuit
Public
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8x3 Encoder

8x3 Encoder
Public
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8x3 Encoder

8x3 Encoder
Public
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8x3 encoder(exp7)

8x3 encoder(exp7)
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8x3 encoder(exp7)

8x3 encoder(exp7)
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8X3 ENCODER

8X3 ENCODER
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8X3 ENCODER

8X3 ENCODER
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Half-Adder

Half-Adder
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4 bit memory register w/ D Flip Flop

4 bit memory register w/ D Flip Flop
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EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER

EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
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EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER

EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
Public
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EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER

EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
Public
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EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER

EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
Public
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EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER

EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
Public
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EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER

EXPERIMENT 2 - MULTIPLEXER AND DEMULTIPLEXER
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SR Flip Flop

SR Flip Flop
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SR Flip Flop

SR Flip Flop
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SR Flip Flop

SR Flip Flop
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Clocked SR Flip Flop

Clocked SR Flip Flop
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Clocked SR Flip Flop

Clocked SR Flip Flop
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L4

L4
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L4

L4
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1:4 Demultiplexer using logic gates

1:4 Demultiplexer using logic gates
Public
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Computer Architecture - CPU Design

Computer Architecture - CPU Design
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Computer Architecture - CPU Design

Computer Architecture - CPU Design
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SIMPLE COMPUTER

SIMPLE COMPUTER
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SIMPLE COMPUTER

SIMPLE COMPUTER
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(4 to 2) line and (8 to 3) Line Encoders

(4 to 2) line and (8 to 3) Line Encoders
Public
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4X1 MULTIPLEXER

4X1 MULTIPLEXER
Public
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Experiment - 6 4 bit binary Adder/Subtractor

Experiment - 6 4 bit binary Adder/Subtractor
Public
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2 BIT ADD/SUB ALGO

2 BIT ADD/SUB ALGO
Public
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1:4 Demultiplexer using logic gates

1:4 Demultiplexer using logic gates
Public
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Spaghett MK 1

Spaghett MK 1
Public
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Full Adder

Full Adder
Public
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8 bit CPU

8 bit CPU
Public
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4 BIT Memory

4 BIT Memory
Public
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Basic gates using NAND GATE

Basic gates using NAND GATE
Public
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8 bit CPU

8 bit CPU
Public
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Minimal ALU

Minimal ALU
Public
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3 - BIT multiplication algorithum

3 - BIT multiplication algorithum
Public
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5x32 Decoder using a combination of 2x4 Decoder and 3x8 Decoder

5x32 Decoder using a combination of 2x4 Decoder and 3x8 Decoder
Public
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Minimal ALU

Minimal ALU
Public
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(4 to 2) line and (8 to 3) Line Encoders

(4 to 2) line and (8 to 3) Line Encoders
Public
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5x32 Decoder using a combination of 2x4 Decoder and 3x8 Decoder

5x32 Decoder using a combination of 2x4 Decoder and 3x8 Decoder
Public
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BINARY LEFT AND RIGHT SHIFT

BINARY LEFT AND RIGHT SHIFT
Public
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4 bit memory register w/ D Flip Flop

4 bit memory register w/ D Flip Flop
Public
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XNOR GATE using NOR GATE

XNOR GATE using NOR GATE
Public
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4-bit parallel adder/subtractor

4-bit parallel adder/subtractor
Public
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CPU Microprocessor

CPU Microprocessor
Public
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SAP - 1

SAP - 1
Public
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Spaghett MK 1

Spaghett MK 1
Public
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8:3 Encoder

8:3 Encoder
Public
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CPU Microprocessor

CPU Microprocessor
Public
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SAP - 1

SAP - 1
Public
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8 bit CPU

8 bit CPU
Public
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