p1csea

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2-bit adder

left/right shift

inlab_cat

3-bit multiplier

2 bit multiplier

3-bit multiplier attempt 2 [success]

(8 to 3 line) Encoder

3:8 Decoder

JK Flip Flop

Basic gates using NAND GATE

RS FLIP FLOP

INTERNAL DIAGRAM OF 1:8 DEMUX

1*4 Demultiplexer

1 to 2 DEMUX

1:4 Demultiplexer using logic gates

(4 to 2) line and (8 to 3) Line Encoders

D Flip-Flop

General Register Organisation

1 to 8 DEMUX

1;2 DEMULTIPLEXER

4x1 Multiplexer

1:4 Demultiplexer using logic gates