project.name

SHREYA RAJPAL

Member since: 2 years

Educational Institution: Not Entered

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cao lab prac

cao lab prac
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full subtractor using NOR gates

full subtractor using NOR gates
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Half Adder using NOR Gates

Half Adder using NOR Gates
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XOR AND XNOR FROM NAND GATE

XOR AND XNOR FROM NAND GATE
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Half-Adder

Half-Adder
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half adder using nand gates

half adder using nand gates
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full adder using nand gate

full adder using nand gate
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full adder using two half adders

full adder using two half adders
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NOT GATE USING NAND GATE

NOT GATE USING NAND GATE
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half and full subtractor

half and full subtractor
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full subtractor

full subtractor
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Full Subtractor using NAND gate

Full Subtractor using NAND gate
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lab fat practise

lab fat practise
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decrementer

decrementer
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Lab fat 1

Lab fat 1
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LAB challenging task 2

LAB challenging task 2
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exp3

exp3
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exp3

exp3
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April 18

April 18
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challenging-task1

challenging-task1
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lab challenging task 2

lab challenging task 2
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4:1_MUX_20BCA0046

4:1_MUX_20BCA0046
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11 april

11 april
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parallel adder

parallel adder
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HALF SUBTRACTOR USING NAND GATE

HALF SUBTRACTOR USING NAND GATE
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Full Subtractor using NOR Gates

Full Subtractor using NOR Gates
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HALF SUBTRACTOR USING NOR GATE

HALF SUBTRACTOR USING NOR GATE
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Full Subtractor using NAND gate

Full Subtractor using NAND gate
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Collaborator

Collaborator
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CAO assn 5

CAO assn 5
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CAO assn 5

CAO assn 5
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1:4 Demultiplexer using logic gates

1:4 Demultiplexer using logic gates
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Full Adder using NOR Gate

Full Adder using NOR Gate
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SHREYA RAJPAL is not a collaborator of any project.

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