4 bit SIPO

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SR Flip Flop using NOR Gare

SR Flip Flop using NAND gate

4 Bit SIPO

4 Bit PIPO

4Bit SISO Reg

OR Gate

AND Gate

NOT Gate

NAND Gate

NOR Gate

XOR Gate

Minimization of circuits 1

Minimization of circuits 2

(1)NOT GATE Gate Universal using Basic gates

(3)OR Gate Universal gates using Basic gates

(4)NOR Gate Univeersal gate using gates

Full Adder

Half Adder

Half Subtractor

Full subtractor

Dcoder 3*8

(2) AND Gate Universal gates using Basic gates

Binary to Grey Code Converter

Grey code to Binary Converter

Encoder

Design half subtractor using gate

Design half subtractor using gate

4Bit SISO Reg

4 Bit SIPO Circuit

4 Bit PIPO Circuit

in complete

3×8 Decoder

4 bit Parallel Adder Subtractor

4 Bit SISO

4 bit parallel adder

Minimization of Circuit 3

4 bit parallel adder 2

3*8 Decoder

8 bit SISO

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