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BT2OECE071_Manish_Palthiya

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

AND GATE

AND GATE
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NOT GATE

NOT GATE
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OR GATE

OR GATE
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XOR gate

XOR gate
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NOT using NAND

NOT using NAND
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AND USING NAND

AND USING NAND
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OR using NAND

OR using NAND
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EXOR using NAND

EXOR using NAND
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boolean equation with nand gates

boolean equation with nand gates
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8:1 MUX using 2:1 MUX

8:1 MUX using 2:1 MUX
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8:3 ENCODER

8:3 ENCODER
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Untitled

Untitled
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Master slave condition using JK FF

Master slave condition using JK FF
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decade counter

decade counter
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D-FF using JK-FF

D-FF using JK-FF
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JK FLIPFLOP

JK FLIPFLOP
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T FF using JK FF

T FF using JK FF
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Full Adder using NAND

Full Adder using NAND
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Experiment 1:Verifying truth table for gates

Experiment 1:Verifying truth table for gates
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EXP 2 :- OR AND NOT EXOR using NAND

EXP 2 :- OR AND NOT EXOR using NAND
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8:3

8:3
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4-BIT BIDIRECTIONAL SHIFT REGISTER

4-BIT BIDIRECTIONAL SHIFT REGISTER
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8:1 from 2:1 mux

8:1 from 2:1 mux
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4:2 PRIORITY ENCODER

4:2 PRIORITY ENCODER
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2:1 MUX using NAND gates

2:1 MUX using NAND gates
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BT2OECE071_Manish_Palthiya is not a collaborator of any project.

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