project.name

BT20ECE020_TEJA VENKATA RATNA SAI KUMAR_CHAVVA

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

J-K Flipflop

J-K Flipflop
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OR GATE

OR GATE
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NOT Gate

NOT Gate
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AND GATE

AND GATE
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EXOR GATE

EXOR GATE
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NAND GATE

NAND GATE
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NOR GATE

NOR GATE
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DE Morgan Second law

DE Morgan Second law
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DE MORGAN'S FIRST LAW

DE MORGAN'S FIRST LAW
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NOT USING AND GATE

NOT USING AND GATE
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Untitled

Untitled
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AND USING NAND GATE

AND USING NAND GATE
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OR USING NAND

OR USING NAND
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EXOR USING NAND

EXOR USING NAND
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Implementing the boolean functions using minimum NAND gates

Implementing the boolean functions using minimum NAND gates
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Verification of truth table of multiplexers (16x1,8x1)

Verification of truth table of multiplexers (16x1,8x1)
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3:8 Decoder

3:8 Decoder
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Full Adder using NAND gates

Full Adder using NAND gates
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JK TO T

JK TO T
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JK TO D

JK TO D
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BIDIRECTIONAL REGISTER

BIDIRECTIONAL REGISTER
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JK MASTER AND SLAVE

JK MASTER AND SLAVE
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JK Flip flop

JK Flip flop
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AND_GATE_TRUTH_TABLE_VERIFICATION

AND_GATE_TRUTH_TABLE_VERIFICATION
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BT20ECE020_TEJA VENKATA RATNA SAI KUMAR_CHAVVA is not a collaborator of any project.

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