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LAB TASK-1 NOR CIRCUIT
LAB TASK-1 NOR CIRCUIT7 Segment Display
7 Segment Display4*4 Array Multiplier_oe
4*4 Array Multiplier_oePOS
POSCOMMON CATHODE WITH DON'T CARES
COMMON CATHODE WITH DON'T CARESCOMMON ANODE WITH DON'T CARES 16:1 MUX
COMMON ANODE WITH DON'T CARES 16:1 MUXCOMMON ANODE with / without DON'T CARE
COMMON ANODE with / without DON'T CAREfull adder using decoder
full adder using decoderMultiplication
Multiplication1 : 16 demultiplexer
1 : 16 demultiplexer16:1 for F'
16:1 for F'DLCD TASK3 16:1 MUX
DLCD TASK3 16:1 MUX8:1 for F'
8:1 for F'FULL ADDER
FULL ADDERQ1-SEVEN SEGMENT DECODER TO DISPLAY NAME & REG NO
Q1-SEVEN SEGMENT DECODER TO DISPLAY NAME & REG NO4:1 Mux using Logic Gates
4:1 Mux using Logic Gates16:1
16:1LAB TASK-1
LAB TASK-1LAB TASK 2
LAB TASK 2SOP in AND OR INV
SOP in AND OR INV1-bit comparator
1-bit comparatorHalf-Adder
Half-Adder1*1 Bit Multiplier
1*1 Bit MultiplierLAB TASK-2 NAND
LAB TASK-2 NAND2:1 NAND
2:1 NANDSOP
SOP16:1 mux using 2:1 mux
16:1 mux using 2:1 muxactive high sop and pos using 4:16
active high sop and pos using 4:16LAB TASK-2
LAB TASK-216:1 mux using 2:1 mux
16:1 mux using 2:1 muxLAB TASK-2
LAB TASK-24*4 Bit Array Multiplier
4*4 Bit Array Multiplier8:1 for F
8:1 for F2:1 NOR
2:1 NOR2:1 NAND
2:1 NANDQ1-SEVEN SEGMENT DECODER TO DISPLAY NAME & REG NO
Q1-SEVEN SEGMENT DECODER TO DISPLAY NAME & REG NOINTERNAL CIRCUIT OF 1:2 DEMUX USING TWO INPUT NAND GATE
INTERNAL CIRCUIT OF 1:2 DEMUX USING TWO INPUT NAND GATEfull subtractor using mux
full subtractor using muxPOS(OR AND INV)
POS(OR AND INV)4:1 Mux using Logic Gates
4:1 Mux using Logic Gates3:8 DECODER USING 2:4 DECODER
3:8 DECODER USING 2:4 DECODER1*8 Demultiplexer
1*8 DemultiplexerHalf-Adder
Half-AdderMAGNITUDE COMPARATOR
MAGNITUDE COMPARATORDecoder 7 seg CC
Decoder 7 seg CCFULL ADDER
FULL ADDERCOMMON CATHODE WITHOUT DON'T CARE
COMMON CATHODE WITHOUT DON'T CARE4:16 decoder using 2:4 decoders
4:16 decoder using 2:4 decoders7 segment display with common anode
7 segment display with common anode1:4 Demultiplexer using logic gates
1:4 Demultiplexer using logic gates2:1 multiplexer
2:1 multiplexer