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HA DCD
HA DCDhalf adder
half adder8:1 MUX circuit
8:1 MUX circuitHA HS 1 bit Multiplier
HA HS 1 bit Multiplier4:! mux using 2:1 mux
4:! mux using 2:1 muxNAND logic -NOT,AND,OR,XOR logic gates
NAND logic -NOT,AND,OR,XOR logic gateslogic gate
logic gateVerification of TT of Logic gates
Verification of TT of Logic gatesTASK III: Verification of logic gates
TASK III: Verification of logic gatesBE using 8:1 MUX (d as i/p, and a,b,c as select lines)
BE using 8:1 MUX (d as i/p, and a,b,c as select lines)nand nor
nand norhalfadder
halfadderHalfsubtractor
HalfsubtractorLAB TASK-1
LAB TASK-1LAB TASK-2 NAND
LAB TASK-2 NANDLAB TASK 2
LAB TASK 2LAB TASK-2
LAB TASK-2LAB TASK-2
LAB TASK-2LAB TASK-1 NOR CIRCUIT
LAB TASK-1 NOR CIRCUITSOP in AND OR INV
SOP in AND OR INVPOS(OR AND INV)
POS(OR AND INV)dcd_task3i
dcd_task3i16:1 FMUX
16:1 FMUX16:1F'MUX
16:1F'MUX8x1AinMUX
8x1AinMUX8x1FMUX
8x1FMUX8x1FCMUX
8x1FCMUX8x1FDMUX
8x1FDMUX8x1FdAMUX
8x1FdAMUX8x1FdBMUX
8x1FdBMUX8x1FdCMUX
8x1FdCMUX8x1FdDMUX
8x1FdDMUX16x1CCMUX
16x1CCMUX8x1CCXMUX
8x1CCXMUX8x1CCYMUX
8x1CCYMUX8x1CCZMUX
8x1CCZMUXDecoder1
Decoder14X16DECODER
4X16DECODER3X8DECODER
3X8DECODER16:1 mux using 2:1 mux
16:1 mux using 2:1 mux4x16us2x8Decoder
4x16us2x8Decoder2:1 NAND
2:1 NAND2x4DecoderNAND
2x4DecoderNAND2:1 NOR
2:1 NORSOP
SOPPOS
POSAHRN4x16Decoder
AHRN4x16DecoderALRN4x16Decoder
ALRN4x16Decoder16:1
16:116:1 for F'
16:1 for F'8:1 for F
8:1 for F8:1 for F'
8:1 for F'active high sop and pos using 4:16
active high sop and pos using 4:16AHCC4X16DECODER
AHCC4X16DECODERALCCW4X16DECODER
ALCCW4X16DECODERAHXCC4x16Decoder
AHXCC4x16DecoderALXCC4x16Decoder
ALXCC4x16DecoderAHYCC4x16Decoder
AHYCC4x16DecoderALYCC4x16Decoder
ALYCC4x16DecoderAHZCC4x16Decoder
AHZCC4x16DecoderALZCC4x16Decoder
ALZCC4x16DecoderCCWXYZ4x16Decoder
CCWXYZ4x16Decoder7-Segment Decoder REG
7-Segment Decoder REGDCD7SEGNAME
DCD7SEGNAMECathodeSegment7
CathodeSegment7AnodeSegment7
AnodeSegment7