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Sanchita Karmakar

Member since: 2 years

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internal arcitecture of 1:4 demux

internal arcitecture of 1:4 demux
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Untitled

Untitled
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t flipflop

t flipflop
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jk flip flop(using NAND)

jk flip flop(using NAND)
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d flip flop using NAND Gate

d flip flop using NAND Gate
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sr flipflop (using NAND Gate)

sr flipflop (using NAND Gate)
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realization of octal to binary encoder using basi gates

realization of octal to binary encoder using basi gates
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internal arcitecture of 1:4 demux

internal arcitecture of 1:4 demux
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internal architecture of 4:1 mux

internal architecture of 4:1 mux
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implementation of 2 bit comparator circuit

implementation of 2 bit comparator circuit
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implementation of full subtractor by using two half subtractor and an or gate

implementation of full subtractor by using two half subtractor and an or gate
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implement half subtractor

implement half subtractor
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implement full subtractor

implement full subtractor
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odd parity

odd parity
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even parity generator

even parity generator
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jk flip flop(using NAND)

jk flip flop(using NAND)
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internal architecture of 4:1 mux

internal architecture of 4:1 mux
Public
project.name

jk flip flop(using NAND)

jk flip flop(using NAND)
Public
project.name

internal arcitecture of 1:4 demux

internal arcitecture of 1:4 demux
Public
project.name

implementation of full subtractor by using two half subtractor and an or gate

implementation of full subtractor by using two half subtractor and an or gate
Public
project.name
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