project.name

Niket Bahety

Member since: 3 years

Educational Institution: IIEST Shibpur

Country: India

SR flip flop using NAND gates

SR flip flop using NAND gates
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Master Slave JK flipflop

Master Slave JK flipflop
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Edge triggered D flip flop

Edge triggered D flip flop
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2:1 MUX using basic gates

2:1 MUX using basic gates
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8:1 MUX using 2:1 MUX

8:1 MUX using 2:1 MUX
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A'B + BC + AC' using 2 to 1 MUX

A'B + BC + AC' using 2 to 1 MUX
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Full Adder using 3 to 8 decoder

Full Adder using 3 to 8 decoder
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Full Adder using 4:1 MUX

Full Adder using 4:1 MUX
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SR Latch using NAND gates

SR Latch using NAND gates
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3-8 decoder using dual 2-4 decoder

3-8 decoder using dual 2-4 decoder
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D flip flop using NAND gates

D flip flop using NAND gates
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D Latch using NAND gates

D Latch using NAND gates
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2-4 decoder using NAND gates

2-4 decoder using NAND gates
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