Chip-Select to Address Block translation for SRAM module for TRS-80 Model 100, based on 7486 quad xor gate. 

The original sram modules for this computer had 4 2k chips on each module. One /CS_A, /CS_B, /CS_C, or /CS_D selects one of the 2k chips to be active at any given time. 

A modern replacement module with a single 8k sram chip needs to convert the 4 chip-select lines into a single chip-select and 2 address lines to select a 2k block of the 8k chip. 

Input is the 4 /CS_* lines, active low, and only one /CS_* line is active at any one time. 

Output is CE2, A11, A12, all active high. 

Resting/starting/default state: all inputs high (no 2k chips selected), CE2 low (8k chip disabled), A11 and A12 low. 

DIRECTIONS

Toggle any single input low. Only one /CS_* may be low at a time.

Desired output / behavior: When any /CS_* line is low, the output should be CE2 high and 0, 1, or 2 of A11 and A12 high, and each /CS_* gets a unique pattern of A11 and A12. 

github.com/bkw777/Model_T_RAM