Searched Projects

Multiplexers

Digital Combinational Circuits

Gates: NOT,  AND, OR, NAND, NOR, XOR, XNOR

half adder, full adder, multiplexer, demultiplexer

Multiplexer: 2:1 MUX, 4:1 MUX, 8:1 MUX

Implementation of functions and gates with MUX

multiplexer8:1

MULTIPLEXER ALU

Composes a 16-to-1 multiplexer using 74151/74HC151/74HCT151 for the purpose of creating an active low signal when the selected status condition flag is also low.

See also project resources:

• https://github.com/Johnlon/spam-1
• https://hackaday.io/project/166922-spam-1-8-bit-cpu
• https://www.youtube.com/channel/UCG6rvUou0GMLyTbjs4Ro2zg

8x1 multiplexer has 8 data input lines I₀, I₁, I₂, I₃, I₄, I₅, I₆, I₇, 3 select lines S₀, S₁, S₂ and one output, Y.

Truth Table for 8x1 Multiplexer

Data Select Input

Output

Y

S₂

S₁

S₀

0

0

0

I₀

0

0

1

I₁

0

1

0

I₂

0

1

1

I₃

1

0

0

I₄

1

0

1

I₅

1

1

0

I₆

1

1

1

I₇

First multiplexer following tutorial with switched outputs, second multiplexer with universal logic gates (only NAND)

It is a full adder circuit made using multiplexer from basic gates.

Design multiplexer using basic gates,

Boolean function implementation

Multiplexer – Demultiplexer Lab assignemnt for ELT  at Pikes Peak Community College, Instructor Mr. Lynn Sim. 

DEMONSTRATION OF A MULTIPLEXER BY LOGIC GATES

This is a simple digital clock with basic combinational and sequential logic circuits.

It can display seconds, minutes, and hours

Users can set time by clicking the button and using the multiplexer to choose which to change.

Also, the design for the 4bits 7segment display and 3 bits 7segment display is inside.

This is assignment of  lab ECN-252 course for CSE student in 4 th semester

multiplexer

mutiple inputs, single output

this is the implementation of 4 to 1 line multiplexer

this is implementation of 8 to 1 multiplexer

Multiplexer 8 inputs. 2³