Lab 3                    0    14   
  • Author: William

    Project access type: Public

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  • Description: Objective:Using Quartus design and test an 8-bit Right shift register with serial input. The circuit will also have an asynchronous clear. Use D flip-flops in your design (Libraries: primitives  Storage  dff). The CLRN input to the D flip-flop is an active low asynchronous clear. Ensure the output of each D-FF goes to an output so the functionally of the shift register can be verified. Notes about the dff: 1. All 8 Flip-Flop need to share a common clock which is connected to an in.2. The clear is an active low so the shift only works when this input is high. 3. The serial input value is the value read when the clock moves from 0 to 1. Positive edge triggered flip-flop. Ensure your simulation input file sufficiently demonstrates the serial input, shift and asynchronous clear.


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