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Author: Ben
Forked from: shri nidhi/HDL simulation
Project access type: Public
Description:
MODULE HalfAdder(A, B, Sum, Carry);
INPUT A, B;
OUTPUT Sum, Carry;
XOR (Sum, A, B); // Sum = A ⊕ B
AND (Carry, A, B); // Carry = A ∧ B
ENDMODULE;
Created: Jan 10, 2025
Updated: Jan 10, 2025
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