JK flip-flop using D flip-flop.

JK flip-flop using D flip-flop.

T flip-flop using D flip-flop

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iii) F’ = (x+yz)’

v) F(x,y,z) = xy + x’z

iv) F(a,b,c) = a + b’c

1. Prove the logic gates using Circuit Verse Simulator

half adder full adder

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end sem 1st question

end sem viva q2

end sem q3

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week 4 q5

half adder using NOR gate only

w3q2

1. Prove the logic gates using Circuit Verse Simulator

1. Prove the logic gates using Circuit Verse Simulator

USING NAND GATE

implement cvz

implement cvz

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k map

SR latch using NOR gates, NAND gates and enable input

SR latch using NOR gates, NAND gates and enable input