/**

 * This is an autogenerated netlist code from CircuitVerse. Verilog Code can be

 * tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. This is an

 * experimental module and some manual changes make need to be done in order for

 * this to work.

 *

 * If you have any ideas/suggestions or bug fixes, raise an issue

 * on https://github.com/CircuitVerse/CircuitVerse/issues/new/choose

 */

/*

  Element Usage Report

    Input - 9 times

    AndGate - 3 times

    OrGate - 6 times

    DigitalLed - 3 times

    NotGate - 1 times

*/

/*

  Usage Instructions and Tips

    Labels - Ensure unique label names and avoid using verilog keywords

    Warnings - Connect all optional inputs to remove warnings

*/

// Sample Testbench Code - Uncomment to use

/*

module TestBench();

  reg inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8;

  Main DUT0(inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8);

  initial begin

    inp_0 = 0;

    inp_1 = 0;

    inp_2 = 0;

    inp_3 = 0;

    inp_4 = 0;

    inp_5 = 0;

    inp_6 = 0;

    inp_7 = 0;

    inp_8 = 0;

    #15

    #10

    $finish;

  end

endmodule

*/

module Main(inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8);

  input inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8;

  wire and_2_out, or_5_out, not_0_out, and_1_out, and_0_out, or_4_out, or_3_out, or_2_out, or_0_out, or_1_out;

  assign and_2_out = and_1_out & inp_8;

  assign or_5_out = or_4_out | and_2_out;

      always @ (*)

        $display("DigitalLed:or_5_out=%d", or_5_out);

  assign not_0_out = ~inp_7;

  assign and_1_out = not_0_out & inp_6;

  assign and_0_out = inp_6 & inp_7;

  assign or_4_out = and_0_out | inp_6;

  assign or_3_out = or_2_out | inp_5;

      always @ (*)

        $display("DigitalLed:or_3_out=%d", or_3_out);

  assign or_2_out = inp_3 | inp_4;

  assign or_0_out = inp_2 | inp_1;

  assign or_1_out = inp_0 | or_0_out;

      always @ (*)

        $display("DigitalLed:or_1_out=%d", or_1_out);

endmodule