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Rakshitha S

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Experiment 5

Experiment 5
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3-Bit (Full) Adder and Subtractor

3-Bit (Full) Adder and Subtractor
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Experiment 7

Experiment 7
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Basic Logic Gate

Basic Logic Gate
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Implementation of Basic Logic Gate by NAND gate

Implementation of Basic Logic Gate by NAND gate
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Implementation of Basic Logic Gates by NOR gate

Implementation of Basic Logic Gates by NOR gate
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2-Bit (Half) Adder and Subtractor

2-Bit (Half) Adder and Subtractor
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2-Bit (Half) Adder and Subtractor

2-Bit (Half) Adder and Subtractor
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3-Bit (Full) Adder and subtractor

3-Bit (Full) Adder and subtractor
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level 1 encorder and decorder

level 1 encorder and decorder
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EPERMINET 6

EPERMINET 6
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Multiplexer and De-Multiplexer (4.1&1.4)

Multiplexer and De-Multiplexer (4.1&1.4)
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Multiplexer and De-Multiplexer (4.1&1.4) using NAND Gate

Multiplexer and De-Multiplexer (4.1&1.4) using NAND Gate
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