CHAMPAKA J V
Member since: 1 year
Educational Institution: PRESIDENCY UNIVERSITY BANGALORE
Country: India
EXPERIMENT-2
EXPERIMENT-2
Public
EXPERIMENT 2
EXPERIMENT 2
Public
EXPERIMENT-2
EXPERIMENT-2
Public
3-BIT FULL ADDER AND SUB USING NAND ONLY
3-BIT FULL ADDER AND SUB USING NAND ONLY
Public
LEVEL-2 USING NAND ONLY 2BIT HALF ADDER
LEVEL-2 USING NAND ONLY 2BIT HALF ADDER
Public
EXP-1 LOGIC GATES IMPLEMENTATION
EXP-1 LOGIC GATES IMPLEMENTATION
Public
IMPLEMENTATION OF BASIC GATES USING UNIVERSAL GATES
IMPLEMENTATION OF BASIC GATES USING UNIVERSAL GATES
Public
EXP 3 2:1 AND4:1 DE-MULTIPLEXER
EXP 3 2:1 AND4:1 DE-MULTIPLEXER
Public
EXPERIMENT-3 2:1 AND4:1 MUX USING BASIC AND NAND GATES
EXPERIMENT-3 2:1 AND4:1 MUX USING BASIC AND NAND GATES
Public
EXPERIMENT-5 AIM1
EXPERIMENT-5 AIM1
Public
EXP 5
EXP 5
Public
EXP-4 ENCODER AND DECODER
EXP-4 ENCODER AND DECODER
Public
EXPERIMENT-3 2;1 AND4
EXPERIMENT-3 2;1 AND4
Public
EXP-4 PRIORITY ENCODER
EXP-4 PRIORITY ENCODER
Public
Untitled
Untitled
Public
EXP-3
EXP-3
Public
EXP-6 LEVEL 1 STUDY OF FLIP FLOP
EXP-6 LEVEL 1 STUDY OF FLIP FLOP
Public
EXP 6 LEVEL 1 NAND BASED FIP FLOP
EXP 6 LEVEL 1 NAND BASED FIP FLOP
Public
EXP-6, LEVEL-2 CONVERSION OF FLIP FLOP
EXP-6, LEVEL-2 CONVERSION OF FLIP FLOP
Public
EXP-8 ASYNCHRONOUS COUNTER CIRCUIT
EXP-8 ASYNCHRONOUS COUNTER CIRCUIT
Public
Experiment 7 Synchronous Counter
Experiment 7 Synchronous Counter
Public
IMPLEMENTATION OF BASIC GATES USING UNIVERSAL GATES
IMPLEMENTATION OF BASIC GATES USING UNIVERSAL GATES
Public
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