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I have a simple circuit using some latches and tri-state drivers. On one clock, I get a stack overflow message but it is not obvious why. The fault occurs when the WR input is manually toggled from 0 to 1. The Verilog text is here: /** * This is an autogenerated netlist code from CircuitVerse. Verilog Code can be * tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. This is an * experimental module and some manual changes make need to be done in order for * this to work. * * If you have any ideas/suggestions or bug fixes, raise an issue * on https://github.com/CircuitVerse/CircuitVerse/issues/new/choose */

/* Element Usage Report Input - 6 times TriState - 2 times Splitter - 3 times Output - 8 times AndGate - 8 times TflipFlop - 8 times OrGate - 1 times NotGate - 1 times ConstantVal - 1 times */

/* Usage Instructions and Tips Labels - Ensure unique label names and avoid using verilog keywords Warnings - Connect all optional inputs to remove warnings */

// Sample Testbench Code - Uncomment to use

/* module TestBench();

reg OE, WR, INC, CLR, inp5; reg [7:0] inp4;

wire D0, D1, D2, D3, D4, D5, D6, D7;

IAR DUT0(D0, D1, D2, D3, D4, D5, D6, D7, OE, WR, INC, CLR, inp4, inp5);

initial begin OE = 0; WR = 0; INC = 0; CLR = 0; inp4 = 0; inp5 = 0;

#15
$display("D0 = %b", D0);
$display("D1 = %b", D1);
$display("D2 = %b", D2);
$display("D3 = %b", D3);
$display("D4 = %b", D4);
$display("D5 = %b", D5);
$display("D6 = %b", D6);
$display("D7 = %b", D7);

#10
$display("D0 = %b", D0);
$display("D1 = %b", D1);
$display("D2 = %b", D2);
$display("D3 = %b", D3);
$display("D4 = %b", D4);
$display("D5 = %b", D5);
$display("D6 = %b", D6);
$display("D7 = %b", D7);

$finish;

end endmodule

*/

module IAR(D0, D1, D2, D3, D4, D5, D6, D7, OE, WR, INC, CLR, inp4, inp5); output D0, D1, D2, D3, D4, D5, D6, D7; input OE, WR, INC, CLR, inp5; input [7:0] inp4; wire and7out, TflipFlop5Q, and0out, TflipFlop4Q, TflipFlop4Qinv, and1out, TflipFlop3Q, TflipFlop3Qinv, and2out, TflipFlop6Q, TflipFlop6Qinv, and3out, TflipFlop1Q, TflipFlop1Qinv, and4out, TflipFlop0Q, TflipFlop0Qinv, and5out, TflipFlop7Q, TflipFlop7Qinv, and6out, TflipFlop2Q, TflipFlop2Qinv, or0out, not0out, const0; wire [7:0] TriState0out, Splitter2cmb; assign TriState0out = (inp5!=0) ? inp4 : 8'b?;

assign D7 = TriState0out[7]; assign D6 = TriState0out[6]; assign D5 = TriState0out[5]; assign D4 = TriState0out[4]; assign D3 = TriState0out[3]; assign D2 = TriState0out[2]; assign D1 = TriState0out[1]; assign D0 = TriState0out[0];

assign and7out = not0out & TriState0out[7]; TflipFlop TflipFlop5(TflipFlop5Q, , TflipFlop4Qinv, const0, or0out, and7out, const0); assign Splitter2cmb = {TflipFlop5Q,TflipFlop4Q,TflipFlop3Q,TflipFlop6Q,TflipFlop1Q,TflipFlop0Q,TflipFlop7Q,TflipFlop2Q}; assign TriState0out = (OE!=0) ? Splitter2cmb : 8'b?; assign and0out = not0out & TriState0out[6]; TflipFlop TflipFlop4(TflipFlop4Q, TflipFlop4Qinv, TflipFlop3Qinv, const0, or0out, and0out, const0); assign and1out = not0out & TriState0out[5]; TflipFlop TflipFlop3(TflipFlop3Q, TflipFlop3Qinv, TflipFlop6Qinv, const0, or0out, and1out, const0); assign and2out = not0out & TriState0out[4]; TflipFlop TflipFlop6(TflipFlop6Q, TflipFlop6Qinv, TflipFlop1Qinv, const0, or0out, and2out, const0); assign and3out = not0out & TriState0out[3]; TflipFlop TflipFlop1(TflipFlop1Q, TflipFlop1Qinv, TflipFlop0Qinv, const0, or0out, and3out, const0); assign and4out = not0out & TriState0out[2]; TflipFlop TflipFlop0(TflipFlop0Q, TflipFlop0Qinv, TflipFlop7Qinv, const0, or0out, and4out, const0); assign and5out = not0out & TriState0out[1]; TflipFlop TflipFlop7(TflipFlop7Q, TflipFlop7Qinv, TflipFlop2Qinv, const0, or0out, and5out, const0); assign and6out = not0out & TriState0out[0]; TflipFlop TflipFlop2(TflipFlop2Q, TflipFlop2Qinv, INC, const0, or0out, and6out, const0); assign or0out = WR | CLR; assign not0out = ~CLR; assign const_0 = 1'b1; endmodule

    module TflipFlop(q, q_inv, clk, t, a_rst, pre, en);
      parameter WIDTH = 1;
      output reg [WIDTH-1:0] q, q_inv;
      input clk, a_rst, pre, en;
      input [WIDTH-1:0] t;

      always @ (posedge clk or posedge a_rst)
        if (a_rst) begin
          q <= 'b0;
          q_inv <= 'b1;
        end else if (en == 0) ;
        else if (t) begin
          q <= q ^ t;
          q_inv <= ~q ^ t;
        end
    endmodule