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Problem with simple circuit getting "stack overflow"

General • Asked 5 days ago by Kurt Zierhut

Kurt Zierhut Commented on Jan 13, 2022:

I have a simple circuit using some latches and tri-state drivers.
On one clock, I get a stack overflow message but it is not obvious why.
The fault occurs when the WR input is manually toggled from 0 to 1.
The Verilog text is here:
/**
* This is an autogenerated netlist code from CircuitVerse. Verilog Code can be
* tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. This is an
* experimental module and some manual changes make need to be done in order for
* this to work.
*
* If you have any ideas/suggestions or bug fixes, raise an issue
* on https://github.com/CircuitVerse/CircuitVerse/issues/new/choose
*/

/*
Element Usage Report
Input - 6 times
TriState - 2 times
Splitter - 3 times
Output - 8 times
AndGate - 8 times
TflipFlop - 8 times
OrGate - 1 times
NotGate - 1 times
ConstantVal - 1 times
*/

/*
Usage Instructions and Tips
Labels - Ensure unique label names and avoid using verilog keywords
Warnings - Connect all optional inputs to remove warnings
*/

// Sample Testbench Code - Uncomment to use

/*
module TestBench();

reg OE, WR, INC, CLR, inp_5;
reg [7:0] inp_4;

wire D0, D1, D2, D3, D4, D5, D6, D7;

IAR DUT0(D0, D1, D2, D3, D4, D5, D6, D7, OE, WR, INC, CLR, inp_4, inp_5);

initial begin
OE = 0;
WR = 0;
INC = 0;
CLR = 0;
inp_4 = 0;
inp_5 = 0;

#15
$display("D0 = %b", D0);
$display("D1 = %b", D1);
$display("D2 = %b", D2);
$display("D3 = %b", D3);
$display("D4 = %b", D4);
$display("D5 = %b", D5);
$display("D6 = %b", D6);
$display("D7 = %b", D7);

#10
$display("D0 = %b", D0);
$display("D1 = %b", D1);
$display("D2 = %b", D2);
$display("D3 = %b", D3);
$display("D4 = %b", D4);
$display("D5 = %b", D5);
$display("D6 = %b", D6);
$display("D7 = %b", D7);

$finish;

end
endmodule

*/

module IAR(D0, D1, D2, D3, D4, D5, D6, D7, OE, WR, INC, CLR, inp_4, inp_5);
output D0, D1, D2, D3, D4, D5, D6, D7;
input OE, WR, INC, CLR, inp_5;
input [7:0] inp_4;
wire and_7_out, TflipFlop_5_Q, and_0_out, TflipFlop_4_Q, TflipFlop_4_Q_inv, and_1_out, TflipFlop_3_Q, TflipFlop_3_Q_inv, and_2_out, TflipFlop_6_Q, TflipFlop_6_Q_inv, and_3_out, TflipFlop_1_Q, TflipFlop_1_Q_inv, and_4_out, TflipFlop_0_Q, TflipFlop_0_Q_inv, and_5_out, TflipFlop_7_Q, TflipFlop_7_Q_inv, and_6_out, TflipFlop_2_Q, TflipFlop_2_Q_inv, or_0_out, not_0_out, const_0;
wire [7:0] TriState_0_out, Splitter_2_cmb;
assign TriState_0_out = (inp_5!=0) ? inp_4 : 8'b?;

assign D7 = TriState_0_out[7];
assign D6 = TriState_0_out[6];
assign D5 = TriState_0_out[5];
assign D4 = TriState_0_out[4];
assign D3 = TriState_0_out[3];
assign D2 = TriState_0_out[2];
assign D1 = TriState_0_out[1];
assign D0 = TriState_0_out[0];

assign and_7_out = not_0_out & TriState_0_out[7];
TflipFlop TflipFlop_5(TflipFlop_5_Q, , TflipFlop_4_Q_inv, const_0, or_0_out, and_7_out, const_0);
assign Splitter_2_cmb = {TflipFlop_5_Q,TflipFlop_4_Q,TflipFlop_3_Q,TflipFlop_6_Q,TflipFlop_1_Q,TflipFlop_0_Q,TflipFlop_7_Q,TflipFlop_2_Q};
assign TriState_0_out = (OE!=0) ? Splitter_2_cmb : 8'b?;
assign and_0_out = not_0_out & TriState_0_out[6];
TflipFlop TflipFlop_4(TflipFlop_4_Q, TflipFlop_4_Q_inv, TflipFlop_3_Q_inv, const_0, or_0_out, and_0_out, const_0);
assign and_1_out = not_0_out & TriState_0_out[5];
TflipFlop TflipFlop_3(TflipFlop_3_Q, TflipFlop_3_Q_inv, TflipFlop_6_Q_inv, const_0, or_0_out, and_1_out, const_0);
assign and_2_out = not_0_out & TriState_0_out[4];
TflipFlop TflipFlop_6(TflipFlop_6_Q, TflipFlop_6_Q_inv, TflipFlop_1_Q_inv, const_0, or_0_out, and_2_out, const_0);
assign and_3_out = not_0_out & TriState_0_out[3];
TflipFlop TflipFlop_1(TflipFlop_1_Q, TflipFlop_1_Q_inv, TflipFlop_0_Q_inv, const_0, or_0_out, and_3_out, const_0);
assign and_4_out = not_0_out & TriState_0_out[2];
TflipFlop TflipFlop_0(TflipFlop_0_Q, TflipFlop_0_Q_inv, TflipFlop_7_Q_inv, const_0, or_0_out, and_4_out, const_0);
assign and_5_out = not_0_out & TriState_0_out[1];
TflipFlop TflipFlop_7(TflipFlop_7_Q, TflipFlop_7_Q_inv, TflipFlop_2_Q_inv, const_0, or_0_out, and_5_out, const_0);
assign and_6_out = not_0_out & TriState_0_out[0];
TflipFlop TflipFlop_2(TflipFlop_2_Q, TflipFlop_2_Q_inv, INC, const_0, or_0_out, and_6_out, const_0);
assign or_0_out = WR | CLR;
assign not_0_out = ~CLR;
assign const_0 = 1'b1;
endmodule

module TflipFlop(q, q_inv, clk, t, a_rst, pre, en);
parameter WIDTH = 1;
output reg [WIDTH-1:0] q, q_inv;
input clk, a_rst, pre, en;
input [WIDTH-1:0] t;

always @ (posedge clk or posedge a_rst)
if (a_rst) begin
q <= 'b0;
q_inv <= 'b1;
end else if (en == 0) ;
else if (t) begin
q <= q ^ t;
q_inv <= ~q ^ t;
end
endmodule