Ask A Question

Subscribe You’re not receiving notifications from this thread.

How do I implement a negative edge triggered JK Flip Flop?

General • Asked 6 months ago by BYSANI R NAVANEETH

Gravatar BYSANI R NAVANEETH Commented on Apr 30, 2021:

The default Flip Flop is positive edge triggered, but I need a negative edge triggered flip flop. How can I implement that?

Gravatar Cupid Stunt Commented on Jun 19, 2021:

Split your clock off in two.
One one line put a buffer and nothing on the other.
Join them with an and gate.
The creates a variable delay that's equal to the sum of the delays of the buffer and the and gate. change the buffer delay to sync it's output with the falling edge of the clock. Put this inline with the positive edge triggered circuit and you're good to go.

Gravatar PRL Commented on Jul 27, 2021:

Just connect your trigger signal to the input of an inverter (NOT gate), then connect the inverter’s output to the D flip-flip’s CLK input.

The flip-flop will now be triggered when your trigger signal changes from high to low.