Example:
Subcircuit verilog Halfadder
module HalfAdder (a,b,s,c);
input a,b;
output s,c;
wire nand_2_out_0,nand_3_out_0,nand_0_out_0,not_0_out_0,nand_1_out_0;
nand nand_2 (nand_2_out_0,nand_0_out_0,b);
nand nand_3 (nand_3_out_0,nand_1_out_0,nand_2_out_0);
assign s = nand_3_out_0;
nand nand_0 (nand_0_out_0,a,b);
not not_0 (not_0_out_0,nand_0_out_0);
assign c = not_0_out_0;
nand n...
Created by Cesar Andrey Perdomo• 3 years ago
General